Application-specific integrated circuits (ASICs), have been supplanted more and more by integrated circuits (ICs) that can be programmed to fulfill multiple functions. There are now many various programmable logic architectures, including, for example, programmable logic devices (“PLDs”), programmable logic arrays (“PLAs”), complex programmable logic devices (“CPLDs”), field programmable gate arrays (“FPGAs”) and programmable array logic (“PALs”). Although there are differences between these various architectures, each of the architectures typically include a set of input conductors coupled as inputs to an array of logic whose outputs, in turn, act as inputs to another portion of the logic device. Complex Programmable Logic Devices (“CPLDs”) are large scale PLDs that, like many programmable architectures, are configured to the specific requirements of an application by programming.
Previously, a device was programmed once for a specific function which would be its only function for its lifetime. Each of these architectures, though, has begun to be implemented in a reprogrammable form. A programmable logic device can now be reprogrammed while in operation and can fulfill the functions of many different devices. One of the more complex reprogrammable logic devices is the programmable-system-on-chip, or PSoC™, which can be implemented as any of a number of devices, anywhere from simple logic gates to those as complex as microcontrollers.
It is noted here that this discussion of the background of the present invention uses the term “PSoC™” extensively. PSoC™ is a registered trademark of Cypress Semiconductor Corp. However, the use of the terms “PSoC” or “PSoC™”, each time they are used, is meant to include all forms of complex programmable and reprogrammable logic device architectures, including PLD, PLA, CPLD, FPGA and PAL.
Programmable devices continue to expand capability to applications previously retained for ASICs. These new applications include such specialized areas as digital signal processing (DSP) and hybrid (analog and digital devices on the same chip), which can be implemented as any of a number of devices, anywhere from simple logic gates to those as complex as microcontrollers.
One of the most demanding applications for a programmable logic array, such as PSoC™, is in the area of digital signal processing, or DSP. DSP requires that both analog and digital functions be accommodated in processing hardware, extremely rapidly, on the same chip. This is limited by the structures achievable in known semiconductor manufacturing processes. Previous generations of PSoC™ have provided a number of analog and digital, reconfigurable, PSoC™ blocks. However, due to the nature of digital reconfigurable PSoC blocks, the previous architectures have not performed digital filtering and other DSP functions well, if at all.
Some previous techniques for accomplishing DSP have used the same processor for both DSP and other functions. Detrimentally, when some complex mathematical functions have had to be performed by the main microprocessor, it has been taken away from other crucial functions.
It can be difficult to accomplish real-time DSP if the main processor is too heavily multi-tasked. Often the processor is needed to perform some necessary DSP computations but is also required for critical control functions and the DSP function performance must be delayed.
The conventional modern processors involved in complex calculations tend to be very large and to be enabled to perform many extra functions. To do so they must be run fast, necessitating ungainly bit-level programming when configuring for DSP functions.
Typically, DSP requires that relatively high speed analog signals be converted to digital equivalents prior to being brought into a processor chip for filtering, decimation (sampling rate reduction), or other intended functions. This multi-step process can put extra demands on a central processor and can entail adverse speed degradation. Additionally, requiring separate semiconductor devices to accomplish different DSP functions also necessitates using up valuable device real estate and limits miniaturization of the end products.
A need exists, therefore, for a configurable, device that accommodates real-time digital signal processing. Furthermore, such a device and its configuration must be user-friendly, enabling a user of normal skills to rapidly configure enormously complex programmable devices with multiple configurations.